1. Field of the Invention
The present invention relates to an integrated circuit and a corresponding manufacturing method.
2. Description of the Related Art
Although in principle applicable to arbitrary integrated circuit devices, the following invention and the underlying problems will be explained with respect to integrated DRAM memory circuits in silicon technology, in particular, DRAM technology which is scaled down to below 100 nm generation and provides big challenges.
DRAM memory circuits of today usually comprise stripe-like active areas, e.g. fabricated in silicon, separated by STI insulation trenches filled with a dielectric material such as silicon oxide.
With feature sizes that are becoming smaller and smaller and nowadays are well below 100 nm, it becomes a challenging task to form memory cells with minimum spatial extension, e.g. 4F2, where F is the critical dimension of the used patterning technology. Also contact etching and etching mask openings for grooves for EUD (Extended U-Groove Device) transistors in the active area stripes between adjacent memory cell capacitors in a manner which is reliable and reproducible in mass production becomes more and more difficult.